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Formazione

Formazione (319)

Oltre 300 corsi sui temi di:
Business Management
Information & Communication Technology

 

I corsi presenti nel Catalogo non esauriscono la nostra capacità di rispondere - con progetti ad hoc - alle diverse esigenze formative.
Contattaci e saremo lieti di darti informazioni, consigli, suggerimenti, preventivi.
Tel: +39 0862.452.401
mail: corsi@ssgrr.com

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Seminari e Eventi

Seminari e Eventi (1)

I Seminari Reiss Romoli sono appuntamenti, di durata di uno o due giorni, per approfondire temi emergenti d'interesse.
Un'occasione di confronto con gli esperti di rilievo nazionale e internazionale.

 
Gli Eventi Reiss Romoli affrontano un tema nei suoi aspetti tecnici e e manageriali.
Sono, generalmente, strutturati in modo da dare ai partecipanti la possibilità di scegliere un percorso individuale tra diverse sessioni didattiche.

 

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Laboratori

Laboratori (0)

I nostri uffici e i laboratori che, per dimensioni e caratteristiche, sono tra i più ricchi e completi nel panorama nazionale, sono all’Aquila.

Usiamo questa risorsa preziosa nella maggior parte dei corsi tecnici e sempre nella preparazione agli esami per conseguire le certificazioni Cisco e Juniper. Sono il nostro strumento didattico di punta. Oltre 300 apparati di rete (Router, Switch per LAN e Data Center, Firewall, Access Point Wireless, telefoni IP, etc.), con più di 50 tra Server e Personal Computer per dare ai partecipanti dei nostri corsi la possibilità di mettere in pratica quanto apprendono in aula.

Accessibilità

I laboratori sono a L’Aquila, ma è possibile accedere da qualunque luogo, basta avere una connessione internet per raggiungere la consolle degli apparati “da remoto” e avere le stesse funzionalità di quando siamo in sede. In questo modo possiamo:

·         realizzare corsi tradizionali teorico/pratici da qualunque aula dotata di PC e di una connessione Internet veloce;

·         svolgere sessioni pratiche di laboratorio nell’ambito di attività di formazione on-line, con l’assistenza di tutor e di esperti;

·         fornire, a singoli o a gruppi di studenti, l’accesso agli apparati per la preparazione, anche non assistita, agli esami di certificazione Cisco e Juniper.

I nostri allievi possono, in scenari di rete uguali a quelli reali - e da qualunque luogo - esercitarsi, fare configurazioni, sviluppare, effettuare il troubleshooting.

Le risorse a disposizione dei partecipanti

Quando l’attività si svolge in aula, la classe è organizzata in piccoli gruppi, preferibilmente di due persone. Ogni gruppo ha a disposizione il proprio ambiente operativo dedicato (POD), formato da tutti gli apparati necessari a provare e verificare le configurazioni descritte teoricamente dal docente. Ciascun POD può essere costituito, in funzione del corso, da un numero variabile tra 3 e 14 apparati di rete, sui quali il gruppo di studenti lavora in modo coordinato.

 

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Giovedì, 10 Ottobre 2019 06:30

ACACES 2019

Scritto da

Reconfigurable Multiprocessor Systems-on-Chip

Si è svolta a luglio la 15esima edizione della International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES 2019), organizzata da HiPEAC in collaborazione con TETRAMAX Innovation Action e Eurolab4HPC . Come per le edizioni precedenti, Reiss Romoli ha avuto un ruolo chiave nella organizzazione e gestione dell’evento.

Durante la Summer School i partecipanti seguono 4 corsi, scelti tra i 12 del programma, oltre a un Keynote Speach e a un Invited Talk.

A questa edizione hanno partecipato circa 220 ricercatori provenienti da molte delle università europee ed esperti del settore, con docenti provenienti da rinomate università americane e da industrie di punta del settore.

Diana Göhringer ha tenuto il corsodi Adaptive Dynamic Systems al TU Dresden, Germany. Dal 2013 al 2017 è stata assistente professore e capo del MCA (application-specific Multi-Core Architectures) research group alla Ruhr-University Bochum (RUB), Germany.

 

Reconfigurable Multiprocessor Systems-on-Chip: Hardware Architectures, Design Tools and Runtime Support

The increasing complexity and adaptive dynamic behaviour of cyber-physical systems, such as advanced driver assistance systems (ADAS) or service robotics, require novel embedded hardware/software solutions. In particular, the dynamic behaviour at runtime needs an approach providing adaptation to changing demands in terms of real-time requirements, data throughput, safety and security. One representative example can be found in robotic systems, where changing situations are handled with image processing algorithms for object detection and tracking. Here, besides the change of algorithm, it would also be recommended to change the hardware architecture, e.g. the reconfiguration of accelerators for specific algorithms, in response to changing situations. This feature can be provided by reconfigurable multiprocessor systems-on-chip (MPSoCs), which can adapt the hardware as well as the software to the application requirements and therefore achieve high computational efficiency as well as high flexibility. However, the development, the programming and the operation of such flexible and heterogeneous systems is very complex as the many criteria (performance, power consumption, costs, development time, runtime adaptations, etc.) open a huge design space.

This course is split in three parts. First, basic principles of Multiprocessor Systems-on-Chip including processing elements, communication infrastructure and memory systems are introduced. The second part covers Field Programmable Gate Arrays (FPGAs) and dynamic partial reconfiguration as the basis for reconfigurable computing systems. The third part gives an overview of existing methods and tools for designing and programming such reconfigurable systems and operating system support for managing the runtime adaptations. Throughout the course, several examples of modern reconfigurable systems are presented.

 

Diana Göhringer, TU Dresden

Since April 2017, Diana Göhringer has been professor for adaptive dynamic systems at TU Dresden, Germany. From 2013 to 2017 she was an assistant professor and head of the MCA (application-specific Multi-Core Architectures) research group at the Ruhr-University Bochum (RUB), Germany. She received her PhD and her master degree in Electrical Engineering and Information Technology from the Karlsruhe Institute of Technology (KIT), Germany in 2011 and 2006, respectively. She is author and co-author of over 100 publications in international journals, conferences and workshops. Additionally, she serves as technical programme committee member in several international conferences and workshops. She is reviewer and guest editor of several international journals. Furthermore, she is a member of IEEE, ACM and HIPEAC. Her research interests include Reconfigurable Computing, Multiprocessor Systems-on-Chip (MPSoCs), Networks-on-Chip, Simulators / Virtual Platforms, Hardware-Software-Codesign and Runtime Systems.

 Diana Göhringer
Lunedì, 23 Settembre 2019 05:50

ACACES 2019

Scritto da

Technology Entrepreneurship

Si è svolta a luglio la 15esima edizione della International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES 2019), organizzata da HiPEAC in collaborazione con TETRAMAX Innovation Action e Eurolab4HPC . Come per le edizioni precedenti, Reiss Romoli ha avuto un ruolo chiave nella organizzazione e gestione dell’evento.

Durante la Summer School i partecipanti seguono 4 corsi, scelti tra i 12 del programma, oltre a un Keynote Speach e a un Invited Talk.

A questa edizione hanno partecipato circa 220 ricercatori provenienti da molte delle università europee ed esperti del settore, con docenti provenienti da rinomate università americane e da industrie di punta del settore.

Il dott. Bart Clarysse è titolare della cattedra di Entrepreneurship al ETH Zürich dove insegna Technology Entrepreneurship, Lean Start-Up Methods and Technology Commercialization. Ha contribuito alla Summer School con un corso su:

 

Technology Entrepreneurship

This course gives you an insight into how technologies unfold into commercial activity. Blockchain, the internet of things (IoT), robotics, artificial intelligence (AI), machine learning and so on offer commercial opportunities to found a new venture. However, the potential applications are less clear from a market point of view.

Hence, revenues are not the main focus of these ventures. Novel financing mechanisms such as initial coin offerings (ICOs) and crowdfunding have emerged which provide entrepreneurs with few resources to overcome the lack of revenues.

The challenge which the nascent entrepreneurs face is how to develop a narrative which convinces both financers and co-founders to get off the ground and how to capture the value of what is created.

In complement to these insights, we develop -in teams- practical business cases based upon your own potential business ideas. The focus of these business cases is upon the analysis of the timing of the customer need, the decision as to engage in traditional or novel forms of market research such as design research to test assumptions that are made behind these business ideas versus taking a more experimental route such as the lean startup approach or even engaging in the social mobilization of resources that fit grand societal challenges (e.g. the use of blockchain to install a national crypto-currency).

During these workshops are developed the skills to develop the story of your idea to convince the audience that needs to provide you with the resources to continue.

 

Bart Clarysse, ETH Zürich

Bart Clarysse holds the chair of entrepreneurship at ETH Zürich where he teaches technology entrepreneurship, lean start-up methods and technology commercialization. His research is focused on understanding how nascent industries such as nanotechnology, blockchain, mobile health, IoT unfold over time and which decisions technology entrepreneurs can make to optimize the value capture of their activities or to potentially disrupt existing industry settings. He is also a visiting professor at Imperial College London, where he teaches executive master’s in business administration (MBAs) and executive subjects on corporate entrepreneurship and innovation.

 Bart Clarysse
Martedì, 03 Settembre 2019 18:51

ACACES 2019

Scritto da

Memory Systems for the Heterogeneous Era

Si è svolta a luglio la 15esima edizione della International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES 2019), organizzata da HiPEAC in collaborazione con TETRAMAX Innovation Action e Eurolab4HPC . Come per le edizioni precedenti, Reiss Romoli ha avuto un ruolo chiave nella organizzazione e gestione dell’evento.

Durante la Summer School i partecipanti seguono 4 corsi, scelti tra i 12 del programma, oltre a un Keynote Speach e a un Invited Talk.

A questa edizione hanno partecipato circa 220 ricercatori provenienti da molte delle università europee ed esperti del settore, con docenti provenienti da rinomate università americane e da industrie di punta del settore.

Il dott. Aamer Jamel, che è Principal Research Scientist nell’ Architecture Research Group (ARG) di NVIDIA, ha contribuito alla Summer School con un corso su:

 

Memory Systems for the Heterogeneous Era

Emerging high performance computing systems consist of multiple latency optimized processors (e.g., CPUs) and throughput optimized processors (e.g. GPUs) interconnected using a high performance network.

The performance of such heterogeneous systems is directly dependent on the processor memory hierarchy. This course covers the trade-offs when designing a high performing memory hierarchy for CPUs, GPUs, and heterogeneous systems consisting of multiple CPUs and GPUs.

It has been shown that different design constraints yield different solutions when designing the memory hierarchy. The lectures cover fundamental design concepts and state-of-the-art research in virtual memory, cache hierarchy, and main memory systems.
The course also includes personal experiences on commercializing research ideas and also include discussions topics on areas for continued research.

 

Aamer Jaleel, NVIDIA

Aamer Jaleel is a Principal Research Scientist in the Architecture Research Group (ARG) at NVIDIA. Prior to joining NVIDIA, Dr. Jaleel was a Principal Engineer in the Versatile Systems and Simulation Advanced Development (VSSAD) group in Intel. During his decade-long career at Intel, Dr. Jaleel's research work contributed towards enhancement in performance modelling and cache hierarchy improvements of Intel’s next generation microprocessors. Dr. Jaleel received his Ph.D. in Electrical Engineering from the University of Maryland, College Park in 2006. He received his B.S. and M.S. in Computer Engineering, also from the University of Maryland, College Park in 2000 and 2002 respectively. Dr. Jaleel has co-authored more than a dozen patents and over 30 technical publications.

 Aamer Jaleel
Domenica, 11 Agosto 2019 05:16

ACACES 2019

Scritto da

Distributed memory programming and algorithms

Si è svolta a luglio la 15esima edizione della International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES 2019), organizzata da HiPEAC in collaborazione con TETRAMAX Innovation Action e Eurolab4HPC . Come per le edizioni precedenti, Reiss Romoli ha avuto un ruolo chiave nella organizzazione e gestione dell’evento.

A questa edizione hanno partecipato circa 220 ricercatori provenienti da molte delle università europee ed esperti del settore, con docenti provenienti da rinomate università americane e da industrie di punta del settore.

Durante la Summer School i partecipanti seguono 4 corsi, scelti tra i 12 del programma, oltre a un Keynote Speach e a un Invited Talk.

Nell’edizione 2019 di ACACES il prof. Scott Baden, della University of California, San Diego, ha tenuto un corso su:

 

Distributed memory programming and algorithms

Distributed memory computers provide bandwidth, processing, and memory scaling capabilities beyond what can be achieved via coherent shared memory. An important consideration in using distributed memory computers effectively is to keep communication costs low, since processing speeds are outpacing communication rates.


Two important models for programming distributed memory are message passing and RMA (Remote Memory Access). RMA comes in many forms, and benefits from global address space communication, that is generally supported by modern network hardware. RMA is employed in PGAS (Partitioned Global Address Space) models which adds global pointers, and optionally, remote procedure call.

These two capabilities play an important role in reducing communication costs, especially for fine grained and irregular communication patterns.

The course has covered message passing and PGAS programming via two libraries, respectively, MPI and UPC++.

The goal of the lectures has been to build a solid grounding in distributed memory programming and the performance trade-offs in efficient implementation.

Algorithmic studies have been presented, and hybrid hierarchical models have been also discussed, which compose distributed memory programming with programming at the node, e.g. multithreading.

The emphasis has been on maintaining low communication costs, as opposed to optimizing computational performance, which is another topic for study.

 

Scott Baden, Lawrence Berkeley National Laboratory, USA

Scott B. Baden is Group Lead of the Computer Languages and System Software Group in the Computational Research Division at Lawrence Berkeley National Laboratory, and Adjunct Professor of Computer Science and Engineering at the University of California, San Diego, where he was a faculty member for 27 years. He earned his Ph.D. from the University of California, Berkeley in 1987. His research interests are in high performance and scientific computation: domain specific translation, abstraction mechanisms, programming models, run times, and irregular problems.

 Scott Baden
Domenica, 11 Agosto 2019 05:08

ACACES 2019

Scritto da

Different ways to run a startup

Si è svolta a luglio la 15esima edizione della International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES 2019), organizzata da HiPEAC in collaborazione con TETRAMAX Innovation Action e Eurolab4HPC . Come per le edizioni precedenti, Reiss Romoli ha avuto un ruolo chiave nella organizzazione e gestione dell’evento.

A questa edizione hanno partecipato circa 220 ricercatori provenienti da molte delle università europee ed esperti del settore, con docenti provenienti da rinomate università americane e da industrie di punta del settore.

Durante la Summer School i partecipanti seguono 4 corsi, scelti tra i 12 del programma, oltre a un Keynote Speach e a un Invited Talk.

Per l’edizione 2019 di ACACES l’Invited  Talk è stato tenuto dal prof. Erik Hagersten dell’Università di Uppsala, che ha parlato di:

 

Different ways to run a startup

All startups are different, and there is no magic sauce or formula that will guarantee success. Running a traditional startup is also VERY different from running a successful research project. There are, of course, new areas to understand, such as law, taxes, financing, investors, IP, business planning, validation, prototyping, production, marketing and sales. But not even the most basic areas of the research, such as the baseline systems, simulation methodologies and evaluation principles, may hold for a startup.


The most brilliant research ideas can lead to an unsuccessful startup if all areas are not understood and dealt with appropriately. The talk has been on prof. Hagersten ‘s experience in running two startups: one a more traditional startup that attempted to cover all the areas, and the other a scaled-down attempt to avoid most of the areas.

 

Erik Hagersten

Erik Hagersten has moved between industry and academia about ten times. He holds a professor chair in computer architecture at Uppsala University in Sweden since 1999. Prior to this, he was the chief architect for Sun Microsystem's high-end server engineering division in the US 1994-1999. In 2006 he founded Acumem AB, developing new modeling technology for multicore software optimisations. Acumem was acquired by Rogue Wave Software Inc. in 2010. In 2014 he founded Green Cache AB, developing new and efficient tag-less cache architectures. Green Cache was sold in 2018.

At Uppsala, Erik has built up he Uppsala Architecture Research Team, UART (it.uu.se/research/group/uart) – one of the largest architecture research groups in Europe. UART performs research in fast performance modelling technology, compiler technology as well as more traditional computer architecture topics. He is a member of the Royal Swedish Academy of Engineering Sciences (IVA) since 2002.

 
Mercoledì, 31 Luglio 2019 09:39

ACACES 2019

Scritto da

The European Processor Initiative

Si è svolta a luglio la 15esima edizione della International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES 2019), organizzata da HiPEAC in collaborazione con TETRAMAX Innovation Action e Eurolab4HPC . Come per le edizioni precedenti, Reiss Romoli ha avuto un ruolo chiave nella organizzazione e gestione dell’evento.

A questa edizione hanno partecipato circa 220 ricercatori provenienti da molte delle università europee ed esperti del settore, con docenti provenienti da rinomate università americane e da industrie di punta del settore.

Durante la Summer School i partecipanti seguono 4 corsi, scelti tra i 12 del programma, oltre a un Keynote Speach e a un Invited Talk.

Per l’edizione 2019 di ACACES il Keynote Speach è stato tenuto dal prof. Mauro Olivieri, dell’Università La Sapienza di Roma, che ha parlato di:

 

Roadmap towards exascale: the European Processor Initiative

The historical evolution of supercomputing technologies and of embedded computing technologies exhibits a convergence of targets that narrows the gap between such traditionally distant worlds, and paves the way to an extraordinary future societal scenario.

As a consequence, the sovereignty on power-efficient high-performance microprocessor technology has become a transversal strategic capability for the advancement of modern nations. Europe, after years of delay with respect to other advanced regions of the world, has now started a set of initiatives to gain a new leading position in computing technology.

The first large investment in such direction is represented by the European Processor Initiative, a 4-year 26-partner project whose aim is to design and implement a roadmap for a new family of low-power European processors, for extreme scale computing and a range of emerging applications. The initial core drivers of the development are supercomputing, AI for Big Data, and future Automotive systems.

The opening keynote talk of the HiPEAC ACACES School 2019 has addressed the motivation, objectives, timeline, and technical insights of this unprecedented project, also highlighting the opportunities for further developments.

 

Mauro Olivieri, Sapienza University of Rome / BSC

Mauro Olivieri received the Master (Laurea) degree in electronics engineering and the Doctorate degree in electronics and computer engineering from the University of Genoa, Italy, where he was an assistant professor from 1995 to 1998. In 1998 he joined Sapienza University of Rome as an associate professor, teaching Digital Electronics and Digital Integrated System Architectures. His research interests are digital system-on-chip design, microprocessor core design, and digital nano-scale circuits. He was the scientific responsible for Sapienza University for 2 FP7 ENIAC JU European projects, 1 FP7 IAPP European project, 4 PRIN/FIRB national projects, 11 MIUR University Projects, and 8 industrial research contracts. He was a technical expert for the Italian Economic Development Ministry in the “Smart Specialization Strategy” project on the topic “Smart Cities/Communities”. He is an evaluator for the European Commission in the ECSEL Joint Undertaking. He is a visiting researcher at the Barcelona Supercomputing Center, Spain, within the European Processor Initiative project. He authored over 110 papers and a textbook in three volumes on digital VLSI design. He has been a TPC member of IEEE DATE and was General Co-Chair of IEEE/ACM ISLPED’15. He is a senior member of the IEEE.

 Mauro Olivieri
Giovedì, 25 Luglio 2019 08:26

Acaces 2019

Scritto da

ACACES 2019

 

Si è appena conclusa la 15esima edizione della International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES 2019), organizzata da HiPEAC in collaborazione con TETRAMAX Innovation Action e Eurolab4HPC . Come per le edizioni precedenti, Reiss Romoli ha avuto un ruolo chiave nella organizzazione e gestione dell’evento.

Durante la Summer School i partecipanti seguono 4 corsi, scelti tra i 12 del programma, oltre a un Keynote Speach e a un Invited Talk.

A questa edizione hanno partecipato circa 220 ricercatori provenienti da molte delle università europee ed esperti del settore, con docenti provenienti da rinomate università americane e da industrie di punta del settore.

 

 

 

 

 

 

 

 

 

 

 

 

 

Qui di seguito i docenti e il titolo dei corsi

  • Gabriel H.Loh (AMD Research) - Die Stacking Integration: Technologies and Applications
  • Scott Baden (Lawrence Berkeley National Laboratory, USA) - Distributed memory programming and algorithms
  • Hadi Esmaeilzadeh (University of California, San Diego) - Accelerated Machine Intelligence: An Edge to Cloud Continuum
  • Thomas Pawlovski (Micron Technology, Inc.) - Memory Technology and Architecture
  • Sebastian Hack (Saarland University) - Compilers
  • Matthew Ma (Dorsey & Whitney LLP) - Intellectual Property Rights: Protection, Enforcement and Risks
  • Aamer Jaleel (NVIDIA) - Memory Systems for the Heterogeneous Era
  • Jakub Szefer (Yale University, USA) - Processor Architecture Security
  • Bart Clarysse (ETH Zürich) - Technology Entrepreneurship
  • Luca Gammaitoni (Università di Perugia, Italy) - Fundamental limits in the ICT energy consumption
  • Diana Göhringer (TU Dresden) - Reconfigurable Multiprocessor Systems-on-Chip
  • Massimo Vanzi (Italian Angels for Growth) - Funding Innovative Startup in Technology and Science
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